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HA-5002
Data Sheet March 8, 2006 FN2921.11
110MHz, High Slew Rate, High Output Current Buffer
The HA-5002 is a monolithic, wideband, high slew rate, high output current, buffer amplifier. Utilizing the advantages of the Intersil D.I. technologies, the HA-5002 current buffer offers 1300V/s slew rate with 110MHz of bandwidth. The 200mA output current capability is enhanced by a 3 output impedance. The monolithic HA-5002 will replace the hybrid LH0002 with corresponding performance increases. These characteristics range from the 3000k input impedance to the increased output voltage swing. Monolithic design technologies have allowed a more precise buffer to be developed with more than an order of magnitude smaller gain error. The HA-5002 will provide many present hybrid users with a higher degree of reliability and at the same time increase overall circuit performance. For the military grade product, refer to the HA-5002/883 datasheet.
Features
* Voltage Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.995 * High Input Impedance . . . . . . . . . . . . . . . . . . . . . .3000k * Low Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . 3 * Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . 1300V/s * Very Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . 110MHz * High Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . 200mA * Pulsed Output Current . . . . . . . . . . . . . . . . . . . . . . 400mA * Monolithic Construction * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Line Driver * Data Acquistion * 110MHz Buffer * Radara Cable Driver * High Power Current Booster * High Power Current Source * Sample and Holds * Video Products
Ordering Information
PART NUMBER HA2-5002-2 HA2-5002-5 HA3-5002-5 HA3-5002-5Z (Note) HA4P5002-5 HA4P5002-5Z (Note) HA9P5002-5 HA9P5002-5Z (Note) HA9P5002-9 HA9P5002-9Z (Note) PART MARKING HA2-5002-2 HA2-5002-5 HA3-5002-5 HA3-5002-5Z HA4P5002-5 HA4P5002-5Z 50025 50025Z 50029 50029Z TEMP. RANGE (C) -55 to 125 0 to 75 0 to 75 0 to 75 0 to 75 0 to 75 0 to 75 0 to 75 -40 to 85 -40 to 85 PACKAGE 8 Pin Metal Can 8 Pin Metal Can 8 Ld PDIP 8 Ld PDIP* (Pb-free) 20 Ld PLCC 20 Ld PLCC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG. # T8.C T8.C E8.3 E8.3 N20.35 N20.35 M8.15 M8.15 M8.15 M8.15
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003-2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
HA-5002 Pinouts
HA-5002 (PDIP, SOIC) TOP VIEW HA-5002 (PLCC) TOP VIEW
OUT V1+ NC NC NC
HA-5002 (METAL CAN) TOP VIEW
IN 8 V1+ 1 7 V1-
V1+ V2NC IN
1 2 3 4
8 7 6 5
OUT V2+ NC 4 NC V1V2- 5 NC 6 NC 7 NC 8
3
2
1
20
19
18 NC 17 V2+ 16 NC 15 NC 14 NC 9 NC 10 IN 11 NC 12 V113 NC NC 3 4 OUT 5 NC V2+ 2 6 V2-
NOTE: Case Voltage = Floating
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FN2921.11 March 8, 2006
HA-5002
Absolute Maximum Ratings
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 44V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V1+ to V1Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . 200mA Output Current (50ms On, 1s Off) . . . . . . . . . . . . . . . . . . . . 400mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (C/W) JC (C/W) PDIP Package*. . . . . . . . . . . . . . . . . . . 92 N/A Metal Can Package . . . . . . . . . . . . . . . 155 67 PLCC Package. . . . . . . . . . . . . . . . . . . 74 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 157 N/A Max Junction Temperature (Hermetic Packages, Note 1) . . . . . . 175C Max Junction Temperature (Plastic Packages, Note 1) . . . . . . . . 150C Max Storage Temperature Range . . . . . . . . . . . . . . -65C to 150C Max Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . 300C (PLCC and SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Temperature Range HA-5002-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C HA-5002-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C HA-5002-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 175C for the can packages, and below 150C for the plastic packages. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS Offset Voltage Average Offset Voltage Drift Bias Current Input Resistance Input Noise Voltage TRANSFER CHARACTERISTICS Voltage Gain (VOUT = 10V)
VSUPPLY = 12V to 15V, RS = 50, RL = 1k, CL = 10pF, Unless Otherwise Specified TEST CONDITIONS TEMP (C) 25 Full Full 25 Full Full 10Hz-1MHz RL = 50 RL = 100 RL = 1k RL = 1k 25 25 25 25 Full 25 25 RL = 100 RL = 1k, VS = 15V RL = 1k, VS = 12V 25 Full Full 25 Full VIN = 1VRMS, f = 10kHz 25 25 25 25 25 25 To 0.1% 25 HA-5002-2 MIN 1.5 0.980 10 10 10 1.0 TYP 5 10 30 2 3.4 3 18 0.900 0.971 0.995 110 40 10.7 13.5 10.5 220 3 <0.005 20.7 3.6 2 30 1.3 50 MAX 20 30 7 10 10 MIN 1.5 0.980 10 10 10 1.0 HA-5002-5, -9 TYP 5 10 30 2 2.4 3 18 0.900 0.971 0.995 110 40 11.2 13.9 10.5 220 3 <0.005 20.7 3.6 2 30 1.3 50 MAX 20 30 7 10 10 UNITS mV mV V/C A A M VP-P V/V V/V V/V V/V MHz A/mA V V V mA % MHz ns ns % V/ns ns
-3dB Bandwidth AC Current Gain OUTPUT CHARACTERISTICS Output Voltage Swing
VIN = 1VP-P
Output Current Output Resistance Harmonic Distortion TRANSIENT RESPONSE Full Power Bandwidth (Note 3) Rise Time Propagation Delay Overshoot Slew Rate Settling Time
VIN = 10V, RL = 40
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FN2921.11 March 8, 2006
HA-5002
Electrical Specifications
PARAMETER Differential Gain Differential Phase POWER REQUIREMENTS Supply Current Power Supply Rejection Ratio NOTE: Slew Rate 3. FPBW = -------------------------- ; V = 10V . 2V PEAK P AV = 10V 25 Full Full 54 8.3 64 10 54 8.3 64 10 mA mA dB VSUPPLY = 12V to 15V, RS = 50, RL = 1k, CL = 10pF, Unless Otherwise Specified (Continued) TEST CONDITIONS RL = 500 RL = 500 TEMP (C) 25 25 HA-5002-2 MIN TYP 0.06 0.22 MAX MIN HA-5002-5, -9 TYP 0.06 0.22 MAX UNITS % Degrees
Test Circuit and Waveforms
+15V V1+ RS IN V1-15V V2OUT V2+
RL
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE
VIN
VIN
VOUT
VOUT
RS = 50, RL = 100 SMALL SIGNAL WAVEFORMS
RS = 50, RL = 1k SMALL SIGNAL WAVEFORMS
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FN2921.11 March 8, 2006
HA-5002 Test Circuit and Waveforms (Continued)
VIN
VIN
VOUT
VOUT
RS = 50, RL = 100 LARGE SIGNAL WAVEFORMS
RS = 50, RL = 1k LARGE SIGNAL WAVEFORMS
Schematic Diagram
V1+ R8 Q19 R4 Q25 R10 Q9 Q10 R5 Q21 Q11 Q15 Q23 Q24 Q17 Q16 R7 R12 R3 V1IN Q7 Q4 Q27 Q6 R11 OUT RN2 Q5 Q22 Q8 R6 Q14 R2 Q13 RN3 V2Q2 Q26 Q20 Q18 Q3 Q1 R1 Q12 V2+
R9
RN1
Application Information
Layout Considerations
The wide bandwidth of the HA-5002 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance.
Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space.
Power Supply Decoupling
For optimal device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from 0.01 to 0.1F will minimize high frequency variations in supply voltage, while low frequency bypassing requires
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FN2921.11 March 8, 2006
HA-5002
larger valued capacitors since the impedance of the capacitor is dependent on frequency. It is also recommended that the bypass capacitors be connected close to the HA-5002 (preferably directly to the supply pins).
Capacitive Loading
The HA-5002 will drive large capacitive loads without oscillation but peak current limits should not be exceeded. Following the formula I = Cdv/dt implies that the slew rate or the capacitive load must be controlled to keep peak current below the maximum or use the current limiting approach as shown. The HA-5002 can become unstable with small capacitive loads (50pF) if certain precautions are not taken. Stability is enhanced by any one of the following: a source resistance in series with the input of 50 to 1k; increasing capacitive load to 150pF or greater; decreasing CLOAD to 20pF or less; adding an output resistor of 10 to 50; or adding feedback capacitance of 50pF or greater. Adding source resistance generally yields the best results.
Operation at Reduced Supply Levels
The HA-5002 can operate at supply voltage levels as low as 5V and lower. Output swing is directly affected as well as slight reductions in slew rate and bandwidth.
Short Circuit Protection
The output current can be limited by using the following circuit:
VV+ R LIM = ------------------------- = ------------------------I OUTMAX I OUTMAX
V+ IOUTMAX = 200mA (CONTINUOUS) RLIM V2+ OUT IN V1V2RLIM
V1+
V1.8 1.6 MAXIMUM POWER DISSIPATION (W) 1.4 PDIP 1.2 1.0 0.8 0.6 0.4 0.2 0.0 25 45 65 85 105 125 TEMPERATURE (C) QUIESCENT POWER DISSIPATION AT 15V SUPPLIES SOIC CAN
PLCC
T JMAX - T A P DMAX = ------------------------------------------ JC + CS + SA Where: TJMAX = Maximum Junction Temperature of the Device TA = Ambient JC = Junction to Case Thermal Resistance CS = Case to Heat Sink Thermal Resistance SA = Heat Sink to Ambient Thermal Resistance Graph is based on: T JMAX - T A P DMAX = ------------------------------ JA
FIGURE 2. MAXIMUM POWER DISSIPATION vs TEMPERATURE
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FN2921.11 March 8, 2006
HA-5002 Typical Application
+12V V1+ RS 50 VIN V1-12V VOUT V2V2+ RM 50 RL 50 RG -58 VOUT VIN
FIGURE 3. COAXIAL CABLE DRIVER - 50 SYSTEM
Typical Performance Curves
9 6 VOLTAGE GAIN (dB) 3 GAIN 0 -3 PHASE -6 -9 -12 -15 -18 1 10 FREQUENCY (MHz) 100 0 PHASE SHIFT 45 90 135 180 VS = 15V, RS = 50 9 6 VOLTAGE GAIN (dB) 3 0 -3 PHASE -6 -9 -12 -15 -18 1 10 FREQUENCY (MHz) 100 0 45 90 135 180 PHASE SHIFT GAIN VS = 15V, RS = 50
FIGURE 4. GAIN/PHASE vs FREQUENCY (RL = 1k)
FIGURE 5. GAIN/PHASE vs FREQUENCY (RL = 50)
0.994 0.992 0.990 VOLTAGE GAIN (V/V) VOLTAGE GAIN (V/V) 0.988 0.986 0.984 0.982 0.980 0.978 0.976 0.974 -60 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 VOUT = -10V TO +10V VS = 15V
0.998 VS = 15V 0.997 0.996 0.995 0.994 0.993 0.992 0.991 -60 VOUT = 0 TO -10V VOUT = 0 TO +10V
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 6. VOLTAGE GAIN vs TEMPERATURE (RL = 100)
FIGURE 7. VOLTAGE GAIN vs TEMPERATURE (RL = 1k)
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FN2921.11 March 8, 2006
HA-5002 Typical Performance Curves
3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -60 VS = 15V 6 BIAS CURRENT (A) 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C)
(Continued)
7 VS = 15V
OFFSET VOLTAGE (mV)
FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE
FIGURE 9. BIAS CURRENT vs TEMPERATURE
15
VS = 15V, RLOAD = 100 SUPPLY CURRENT (mA)
10 VS = 15V, IOUT = 0mA 9
OUTPUT VOLTAGE (V)
14
+VOUT
8 7 6 5 4
13
-VOUT
12
11 -60
-40
-20
0 20 40 60 TEMPERATURE (C)
80
100
120
3 -60
-40
-20
0 20 40 60 TEMPERATURE (C)
80
100
120
FIGURE 10. MAXIMUM OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 11. SUPPLY CURRENT vs TEMPERATURE
10 IOUT = 0mA 125C, 25C SUPPLY CURRENT (mA) 8 IMPEDANCE () -55C 6 100K
VS = 15V
10K
ZIN
1000
4
100
2 10 0 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V) ZOUT
1 100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 13. INPUT/OUTPUT IMPEDANCE vs FREQUENCY
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FN2921.11 March 8, 2006
HA-5002 Typical Performance Curves
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 15
(Continued)
80 RLOAD = 100 70 60 PSRR (dB) 50 40 30 20 10 0 10K
VOUT MAX, VP-P AT 100kHz
TA = 25C TA = 125C, TA = -55C
12 8 SUPPLY VOLTAGE (V)
5
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 14. VOUT MAXIMUM vs VSUPPLY
FIGURE 15. PSRR vs FREQUENCY
1500 1400 SLEW RATE (V/s) 1300 1200 1100 1000 900 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 VOUT - VIN (mV)
150 100 50 RL = 1K 0 -50
VS = 15V TA = 25C RL = 100
RL = 600 -100 -150 -10
-8
-6
-4 -2 0 2 4 INPUT VOLTAGE (VOLTS)
6
8
10
FIGURE 16. SLEW RATE vs SUPPLY VOLTAGE
FIGURE 17. GAIN ERROR vs INPUT VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): V1TRANSISTOR COUNT: 27 PROCESS: Bipolar Dielectric Isolation
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FN2921.11 March 8, 2006
HA-5002 Metallization Mask Layout
HA-5002
V1IN
V1- (ALT) V1+ (ALT)
V2+
V2-
V1+
OUT
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FN2921.11 March 8, 2006
HA-5002 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 8
2.93
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FN2921.11 March 8, 2006
HA-5002 Metal Can Packages (Can)
REFERENCE PLANE A L L2 L1 A A OD OD1 Oe 2 1 Ob1 F Q Ob BASE AND SEATING PLANE BASE METAL LEAD FINISH N k1 OD2
T8.C MIL-STD-1835 MACY1-X8 (A1)
e1 8 LEAD METAL CAN PACKAGE INCHES SYMBOL A Ob Ob1 Ob2 OD MIN 0.165 0.016 0.016 0.016 0.335 0.305 0.110 MAX 0.185 0.019 0.021 0.024 0.375 0.335 0.160 MILLIMETERS MIN 4.19 0.41 0.41 0.41 8.51 7.75 2.79 MAX 4.70 0.48 0.53 0.61 9.40 8.51 4.06 NOTES 1 1 2 1 1 1 3 3 4 Rev. 0 5/18/94
k
OD1
C L
OD2 e e1 F k k1
0.200 BSC 0.100 BSC 0.027 0.027 0.500 0.250 0.010 45o BSC 45o BSC 8 0.040 0.034 0.045 0.750 0.050 0.045 -
5.08 BSC 2.54 BSC 1.02 0.86 1.14 19.05 1.27 1.14
0.69 0.69 12.70 6.35 0.25
Ob1
Ob2
L L1
SECTION A-A
L2 Q
NOTES: 1. (All leads) Ob applies between L1 and L2. Ob1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. 3. is the basic spacing from the centerline of the tab to terminal 1 and is the basic spacing of each lead or lead position (N -1 places) from , looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH.
N
45o BSC 45o BSC 8
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FN2921.11 March 8, 2006
HA-5002 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP
N20.35 (JEDEC MS-018AA ISSUE A)
0.004 (0.10) C
20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 MIN 0.165 0.090 0.385 0.350 0.141 0.385 0.350 0.141 20 MAX 0.180 0.120 0.395 0.356 0.169 0.395 0.356 0.169 MILLIMETERS MIN 4.20 2.29 9.78 8.89 3.59 9.78 8.89 3.59 20 MAX 4.57 3.04 10.03 9.04 4.29 10.03 9.04 4.29 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97
0.025 (0.64) R 0.045 (1.14)
D2/E2 C L E1 E D2/E2 VIEW "A"
D D1 D2 E E1 E2 N
D1 D 0.020 (0.51) MAX 3 PLCS
A1 A
0.020 (0.51) MIN
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) MIN VIEW "A" TYP.
0.025 (0.64) MIN
NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions.
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FN2921.11 March 8, 2006
HA-5002 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN2921.11 March 8, 2006

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